Field-programmable gate array (fpga) configurable cell with p and n pass gates to same bit line

Abstract

A Field-Programmable Gate Array (FPGA) RAM cell has cross-coupled inverters and transmission gates to bit lines. Each transmission gate has n-channel and p-channel transistors in parallel that both turn on during writing and reading in configuration mode, but remain off for mission mode when the FPGA performs the configured logic functions. For configurable switching fabric, the FPGA RAM cell has nodes from the cross-coupled inverters drive gates of p-channel and n-channel transistors in parallel that form a transmission gate between a switch input and a switch output in the configurable switching fabric. For configurable logic blocks, the FPGA RAM cell has a node from the cross-coupled inverters driving gates of p-channel and n-channel data transistors in a four-transistor stack with p-channel and n-channel select transistors controlled by a logic input. The row of FPGA RAM cells store a Look-Up Table (LUT) and perform first-level muxing.