The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

G11C 7/10 (2006.01); G11C 7/12 (2006.01); G11C 11/16 (2006.01); G11C 13/00 (2006.01); G11C 16/08 (2006.01); G11C 16/12 (2006.01); G11C 16/24 (2006.01); G11C 16/26 (2006.01); G11C 7/06 (2006.01); G11C 16/04 (2006.01);

U.S. Cl.

CPC ...

G11C 7/1063 (2013.01); G11C 7/106 (2013.01); G11C 7/12 (2013.01);

Abstract

Upper bit lines extend along Y direction in an upper memory array and a Y decoder. Lower bit lines extend along Y direction in a lower memory array and the Y decoder. The Y decoder includes an upper Y line selection switch connected to the upper bit lines and a lower Y line selection switch connected to the lower bit lines and disposed at the other side of the upper Y line selection switch along Y direction. A switch circuit is configured to be capable of switching to permit either conduction between a sense amplifier and the upper Y line selection switch or conduction between the sense amplifier and the lower Y line selection switch.

Find Patent Forward Citations

Imai, Takeharu. (2026). Memory device with sub-arrays and selection switches for reducing bit line interference (U.S. Patent No. 12718852). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12718852

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