The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 25, 2026

Filed:

Oct. 28, 2024
Applicant:

Samsung Display Co., Ltd., Yongin-Si, KR;

Inventors:

Minjoo Kim, Yongin-si, KR;

Minwoo Byun, Yongin-si, KR;

Ji-Hyun Ka, Yongin-si, KR;

Assignee:

Samsung Display Co., Ltd., Yongin-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/3266 (2016.01); G09G 3/3233 (2016.01);
U.S. Cl.
CPC ...
G09G 3/3266 (2013.01); G09G 3/3233 (2013.01); G09G 2300/0852 (2013.01); G09G 2300/0861 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0233 (2013.01); G09G 2330/021 (2013.01);
Abstract

A gate driver comprises a plurality of stages. Each of the stages includes a writing selection circuit configured to apply a writing selection signal to a first inversion control node based on the writing selection signal in a writing period, a holding selection circuit configured to apply a holding selection signal to a second inversion control node based on the holding selection signal in a holding period, and a gate output circuit configured to output a first low gate voltage as a low gate voltage in response to a voltage of the first inversion control node in the writing period, and output a second low gate voltage that is different from the first low gate voltage as the low gate voltage in response to a voltage of the second inversion control node in the holding period.


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