Asymmetric multi-level caching structure for efficient data storage and retrieval

Abstract

A hardware-based electronic trading system is disclosed that minimizes external memory accesses, thereby reducing overall latency. Order data for all open orders of a particular symbol, side, and price may be organized into a defined data structure, or tile, that can be fetched from an external memory cache. Once loaded into an internal memory cache of an FPGA or other fixed logic, the tile may be accessed often with minimal delay to obtain order data for multiple open orders having the same symbol, side, and price. To further minimize the number of external memory accesses, external memory can be provisioned as an asymmetric, multi-level memory cache that is tailored for handling large data sets of matching engine books and ticker plant services. In particular, the multi-level memory cache can be implemented using external memory units in the form of DRAMs for storing tiles according to a price priority scheme.