Inline cryptographic engine for storage controllers

Abstract

Various embodiments include methods implemented in an inline cryptographic module of a system on chip (SoC) for inline cryptographic core management. Embodiments may include receiving a cryptographic core configuration request for a data stream of a multi-data stream memory controller, and dynamically configuring at least one cryptographic core for the data stream. Embodiments may include the request being an allocation request for the data stream, activating an available cryptographic core, being the at least one cryptographic core, and allocating the at least one cryptographic core to the data stream. Embodiments may include the request being a deallocation request for the data stream, scanning a plurality of cryptographic cores assigned to the data stream for an indication of an idle state of the at least one cryptographic core, deactivating the at least one cryptographic core, and deallocating the at least one cryptographic core from the data stream.