The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 25, 2026

Filed:

Sep. 27, 2024
Applicant:

Xi'an Jiaotong University, Xi'an, CN;

Inventors:

Tian Xia, Xi'an, CN;

Gelin Fu, Xi'an, CN;

Zhongpei Luo, Xi'an, CN;

Wenzhe Zhao, Xi'an, CN;

Pengju Ren, Xi'an, CN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/08 (2016.01); G06F 9/32 (2018.01); G06F 12/02 (2006.01); G06F 12/0811 (2016.01); G06F 12/0862 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0862 (2013.01); G06F 9/321 (2013.01); G06F 12/0292 (2013.01); G06F 12/0811 (2013.01);
Abstract

A differential matching prefetcher for coping with irregular memory access includes: an access index table, an access target table, a differential matching module, an index queue, an indirect memory access candidate scoreboard, an address generator, an indirect memory access relationship table, a prefetch status handling register, a repetition filter, a continuous address filter, and a range prefetch table. The differential matching prefetcher is configured to monitor events of access requests and data responses between a computing core and a first level of cache, as well as between the first level of cache and a second level of cache. The differential matching prefetcher may be applied in various general-purpose computing architectures adopting a hierarchical storage design to realize mode capture and data prefetch for irregular indirect memory access, reduce long-delay storage access overhead caused by the irregular memory access, and increase instructions per cycle (IPC) of the computing architectures.


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