Concurrent fill and byte merge

Abstract

Systems and techniques for concurrently performing a fill and byte merge operation in a data processing system are described. An example technique includes receiving a memory access request from a user interface. A determination is made that the memory access request has encountered a cache miss within a cache directory in the computing system. In response to the determination, a fetch request is transmitted to an upper level cache within the computing system for a cache line associated with the memory access request. Dirty portions of the cache line are concurrently written and merged, based on the memory access request, with fill data of the cache line obtained from the upper level cache into a line buffer of a line engine within the computing system.