The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 25, 2026

Filed:

Feb. 24, 2023
Applicant:

Microsoft Technology Licensing, Llc, Redmond, WA (US);

Inventors:

Fanny Nina Paravecino, San Jose, CA (US);

Michael Eric Davies, Cedar Rapids, IA (US);

Abhishek Dilip Kulkarni, San Jose, CA (US);

MD Aamir Raihan, Toronto, CA;

Ankit More, San Mateo, CA (US);

Aayush Ankit, Sunnyvale, CA (US);

Torsten Hoefler, Pfaeffikon, SZ;

Douglas Christopher Burger, Bellevue, WA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/50 (2006.01);
U.S. Cl.
CPC ...
G06F 9/5027 (2013.01);
Abstract

Operations of a workload are assigned to physical resources of a physical device array. The workload includes a graph of operations to be performed on a physical device array. The graph of operations is partitioned into subgraphs. Partitioning includes at least minimizing the quantity of subgraphs and maximizing resource utilization per subgraph. A logical mapping of the subgraph to logical processing engine (PE) units is generated using features of the subgraph and tiling factors of the logical PE units. The logical mapping is assigned to physical PE units of the physical device array at least by minimizing network traffic across the physical PE units. The operations of the subgraph are performed using the physical PE units to which the logical mapping is assigned. This process enhances the computational efficiency of the array when executing the workload.


Find Patent Forward Citations

Nina Paravecino, Fanny. (2026). Assigning workloads to physical resources in spatial architectures (U.S. Patent No. 12717631). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12717631

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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