The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 25, 2026

Filed:

Apr. 24, 2023
Applicant:

Nxp B.v., Eindhoven, NL;

Inventors:

Chandan Gupta, Greater Noida, IN;

Shikhar Makkar, Palwal, IN;

Saumya Pandey, Raseda, IN;

Assignee:

NXP B.V., Eindhoven, NL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/317 (2006.01); G06F 1/08 (2006.01); H03K 19/20 (2006.01);
U.S. Cl.
CPC ...
G01R 31/31727 (2013.01); G06F 1/08 (2013.01); H03K 19/20 (2013.01);
Abstract

An integrated circuit (IC), including a clocking system, a plurality of clock gate controllers, and a plurality of clock gates, is provided. During a capture phase of an at-speed testing of the IC, the clocking system generates an at-speed clock signal including launch and capture pulses that are extracted from a reference clock signal based on a capture phase frequency. The plurality of clock gate controllers generates a plurality of enable signals such that for the launch pulse, one enable signal is asserted, and for the capture pulse, the same or different enable signal is asserted. Each of the plurality of clock gates is activated based on an assertion of a corresponding enable signal. Further, during the capture phase, one or more activated clock gates enable the at-speed testing of the IC based on the at-speed clock signal.


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