The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 11, 2026

Filed:

Apr. 07, 2023
Applicant:

Samsung Electronics Co., Ltd, Suwon-si, KR;

Inventors:

Choongbin Yim, Suwon-si, KR;

Gitae Park, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 70/60 (2026.01); H10B 80/00 (2023.01); H10W 70/05 (2026.01); H10W 70/63 (2026.01); H10W 70/685 (2026.01); H10W 74/01 (2026.01); H10W 74/10 (2026.01); H10W 90/00 (2026.01); H10W 72/00 (2026.01); H10W 72/30 (2026.01); H10W 74/15 (2026.01);
U.S. Cl.
CPC ...
H10W 70/635 (2026.01); H10B 80/00 (2023.02); H10W 70/05 (2026.01); H10W 70/611 (2026.01); H10W 70/685 (2026.01); H10W 74/01 (2026.01); H10W 74/117 (2026.01); H10W 90/401 (2026.01); H10W 90/701 (2026.01); H10W 72/072 (2026.01); H10W 72/07354 (2026.01); H10W 72/347 (2026.01); H10W 72/865 (2026.01); H10W 72/884 (2026.01); H10W 74/15 (2026.01); H10W 90/724 (2026.01); H10W 90/732 (2026.01); H10W 90/734 (2026.01); H10W 90/752 (2026.01); H10W 90/754 (2026.01);
Abstract

A semiconductor package includes a first redistribution wiring layer including a first redistribution wiring, a semiconductor chip disposed on the first redistribution wiring layer, a plurality of interposer connectors disposed on the first redistribution wiring layer, each of the plurality of interposer connectors including a first surface facing the first redistribution wiring layer and a second surface opposite the first surface, a plurality of through electrodes and a plurality of core balls formed on the first surface and including a core and a solder layer, the through electrodes being electrically connected to the first redistribution wiring by the core balls, a molding member on the first redistribution wiring layer that covers the semiconductor chip, and a second redistribution wiring layer disposed on the molding member including a second redistribution wiring electrically connected to the through electrodes.


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