The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 11, 2026

Filed:

Jun. 22, 2022
Applicant:

Medtronic, Inc., Minneapolis, MN (US);

Inventors:

Randolph E. Crutchfield, Scottsdale, AZ (US);

Jeff M. Wheeler, Gilbert, AZ (US);

Assignee:

Medtronic, Inc., Minneapolis, MN (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/552 (2006.01); A61N 1/05 (2006.01); A61N 1/375 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H10W 20/00 (2026.01); H10W 20/40 (2026.01); H10W 20/41 (2026.01); H10W 20/43 (2026.01); H10W 42/20 (2026.01); H10W 42/25 (2026.01); A61N 1/36 (2006.01); A61N 1/362 (2006.01); A61N 1/39 (2006.01); H10W 70/654 (2026.01); H10W 70/69 (2026.01);
U.S. Cl.
CPC ...
H10W 42/20 (2026.01); A61N 1/0504 (2013.01); A61N 1/375 (2013.01); H10W 20/0698 (2026.01); H10W 20/074 (2026.01); H10W 20/423 (2026.01); H10W 20/43 (2026.01); H10W 20/495 (2026.01); H10W 42/25 (2026.01); A61N 1/0509 (2013.01); A61N 1/0531 (2013.01); A61N 1/0534 (2013.01); A61N 1/0541 (2013.01); A61N 1/36038 (2017.08); A61N 1/36053 (2013.01); A61N 1/36062 (2017.08); A61N 1/362 (2013.01); A61N 1/3756 (2013.01); A61N 1/3956 (2013.01); H10W 70/654 (2026.01); H10W 70/69 (2026.01);
Abstract

Various embodiments of an integrated circuit package are disclosed. The package includes an integrated circuit having an integrated circuit contact disposed on a first major surface of the integrated circuit; a first passivation layer disposed on the first major surface of the integrated circuit and over the integrated circuit contact; and a redistribution layer disposed on the first passivation layer. The redistribution layer includes a conductive trace and a shield region that define a plane of the redistribution layer. The package further includes a second passivation layer disposed on the redistribution layer, and a patterned conductive layer disposed on the second passivation layer and including a conductive trace. A portion of the shield region of the redistribution layer is disposed between the conductive trace of the patterned conductive layer and the integrated circuit along an axis that is substantially orthogonal to the first major surface of the integrated circuit.


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