logo

For the Inventor, By the Inventor

The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12707959 B1

PDFFull Text
Date of Patent:
Aug. 11, 2026

Filed:

Oct. 26, 2023

Three-dimensional memory device containing dummy via cavities and method for making same

Applicant:

Western Digital Technologies, Inc., San Jose, CA (US);

Inventors:

Daichi Saito, Yokkaichi, JP;

Masaaki Shinohara, Yokkaichi, JP;

Ryo Yoshimoto, Yokkaichi, JP;

Koichi Ito, Yokkaichi, JP;

Assignee:

Sandisk Technologies, Inc., Milpitas, CA (US);

Attorney:

THE MARBURY LAW GROUP PLLC

Primary Examiner:

Khaja Ahmad

Int. Cl.
CPC ...
H10W 20/41 (2026.01); G11C 16/04 (2006.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 41/40 (2023.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01); H10B 43/40 (2023.01); H10W 20/42 (2026.01);
U.S. Cl.
CPC ...
H10W 20/435 (2026.01); G11C 16/0483 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 41/40 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02); H10W 20/42 (2026.01);
Abstract

A semiconductor structure includes a first-tier alternating stack of first-tier insulating layers and first-tier electrically conductive layers, a second-tier alternating stack of second-tier insulating layers and second-tier electrically conductive layers that overlies the first-tier alternating stack, a memory opening vertically extending through the first-tier alternating stack and the second-tier alternating stack, a memory opening fill structure located in the memory opening and including a memory film and a vertical semiconductor channel, a first contact via structure contacting one of the first-tier electrically conductive layers, a first-tier tubular dielectric spacer including a first inner sidewall contacting the first contact via structure and contacting each first-tier electrically conductive layer that overlies said one of the first-tier electrically conductive layers, and a first-tier pillar structure vertically extending through each first-tier electrically conductive layer and having a top surface that is coplanar with a topmost surface of the first-tier alternating stack.

Find Patent Forward Citations

Saito, Daichi. (2026). Three-dimensional memory device containing dummy via cavities and method for making same (U.S. Patent No. 12707959). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12707959

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…