Semiconductor memory device including pad sacrifice films and electronic system including the same

Abstract

A semiconductor memory device includes a peripheral circuit structure including a peripheral circuit substrate, a peripheral circuit element on the peripheral circuit substrate, and a wiring structure connected to the peripheral circuit element and a memory cell structure provided on the peripheral circuit structure. The memory cell structure includes a cell substrate including a cell array region, an extended region, and a through region, a mold structure including a plurality of gate electrodes sequentially provided on the cell array region and on the extended region in a step form, and a plurality of mold sacrifice films sequentially provided on the through region, a channel structure intersecting the plurality of gate electrodes on the cell array region, and a cell contact penetrating the mold structure on the extended region and configured to connect at least one of the plurality of gate electrodes and the wiring structure.