The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 11, 2026

Filed:

Apr. 28, 2022
Applicants:

Chengdu Boe Optoelectronics Technology Co., Ltd., Chengdu, CN;

Boe Technology Group Co., Ltd., Beijing, CN;

Inventors:

Fan He, Beijing, CN;

Rong Wang, Beijing, CN;

Xiangdan Dong, Beijing, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10K 59/131 (2023.01); H10K 59/10 (2023.01); H10K 59/12 (2023.01); H10K 59/121 (2023.01); H10K 59/122 (2023.01);
U.S. Cl.
CPC ...
H10K 59/131 (2023.02); H10K 59/1201 (2023.02); H10K 59/1213 (2023.02); H10K 59/1216 (2023.02); H10K 59/122 (2023.02);
Abstract

A display panel and a manufacturing method therefor, and a display apparatus. The display panel comprises: a drive backplane (BM), a transfer layer (TR), a second planarization layer (PLN), and a light-emitting layer (EE). A pixel circuit layer (DR) comprised in the drive backplane (BM) comprises a plurality of data transfer lines (DL), wherein one end of a data transfer line (DL) is connected to a data wiring (DL) and the other end thereof extends to a bonding region (B). Two ends of a first transfer line (TR) comprised in the transfer layer (TR) are respectively connected to a first via hole (PLN) and a second via hole (PLN) that correspond to a first pixel circuit (PDCA).


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