The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 11, 2026

Filed:

Feb. 15, 2024
Applicant:

Lg Display Co., Ltd., Seoul, KR;

Inventors:

Min-June Jang, Paju-si, KR;

Miyoung Son, Paju-si, KR;

Hongjae Shin, Paju-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); G09G 3/3233 (2016.01); G09G 3/3266 (2016.01); H10D 86/40 (2025.01); H10D 86/60 (2025.01);
U.S. Cl.
CPC ...
H10D 86/60 (2025.01); G09G 3/3233 (2013.01); G09G 3/3266 (2013.01); H10D 86/443 (2025.01); G09G 2300/0408 (2013.01); G09G 2300/0413 (2013.01); G09G 2300/0819 (2013.01); G09G 2300/0842 (2013.01); G09G 2310/0291 (2013.01); G09G 2330/04 (2013.01);
Abstract

A display panel comprises a substrate including a display area where a plurality of subpixels are disposed, a gate driving circuit disposed in a non-display area outside the display area to supply a plurality of scan signals to the plurality of subpixels, and a plurality of pads disposed in the non-display area and coupled with a plurality of signal lines electrically connected to the gate driving circuit and an electrostatic discharge unit, wherein the plurality of pads include a clock pad connected with a clock signal line, a first line pad connected with a plurality of first power lines and where at least one low-potential signal line is disposed between adjacent gate high-potential voltage lines among the plurality of first power lines, and a second line pad connected with a plurality of second power lines.


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