Semiconductor device with cmos inverter

Abstract

A semiconductor device includes a buried insulation layer pattern on a lower substrate. A first semiconductor pattern and a second semiconductor pattern pattern are disposed on on the buried insulation layer pattern. A lower conductive pattern is formed in a lower portion of a first recess between the first and second semiconductor patterns, and the lower conductive pattern may contact lower sidewalls of the first and second semiconductor patterns. A common gate structure formed on the lower conductive pattern fills a remaining portion of the first recess. The first semiconductor pattern may include a first impurity region, a first channel region, and a second impurity region sequentially stacked from an upper surface of the first semiconductor towards the lower substrate. The second semiconductor pattern includes a third impurity region, a second channel region, and a fourth impurity region.