The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 11, 2026

Filed:

Jun. 30, 2023
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Seongheum Choi, Suwon-si, KR;

Chunghwan Shin, Suwon-si, KR;

Rakhwan Kim, Suwon-si, KR;

Yeji Song, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/62 (2025.01); H10D 30/00 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 64/23 (2025.01); H10D 64/62 (2025.01); H10D 84/01 (2026.01); H10D 84/83 (2025.01); H10D 30/01 (2025.01);
U.S. Cl.
CPC ...
H10D 30/6219 (2025.01); H10D 30/508 (2025.01); H10D 30/6211 (2025.01); H10D 62/121 (2025.01); H10D 64/017 (2025.01); H10D 64/256 (2025.01); H10D 64/62 (2025.01); H10D 84/0158 (2025.01); H10D 84/83125 (2025.01); H10D 84/832 (2025.01); H10D 84/834 (2025.01); H10D 30/019 (2025.01); H10D 30/024 (2025.01);
Abstract

A semiconductor device includes: an active fin disposed on a substrate and protruding from an upper surface of the substrate; a gate structure disposed on the active fin; a source/drain layer disposed on a portion of the active fin adjacent to the gate structure; an ohmic contact pattern on the source/drain layer; and a contact plug disposed on an upper surface of the ohmic contact pattern, wherein the contact plug includes: a conductive structure including a metal; and a barrier pattern covering a lower surface and a sidewall of the conductive structure, wherein a thickness of the barrier pattern is equal to or less than about 10 Å, and wherein a maximum diameter of a grain of the metal included in the conductive structure is in a range of about 8 nm to about 15 nm.


Find Patent Forward Citations

Loading…