The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 11, 2026

Filed:

Sep. 27, 2022
Applicant:

SK Hynix Inc., Icheon-si, KR;

Inventors:

Jin Ho Bin, Icheon-si, KR;

Chul Young Kim, Icheon-si, KR;

Ji Yeon Baek, Icheon-si, KR;

Sul Gi Jung, Icheon-si, KR;

Assignee:

SK hynix Inc., Icheon-si, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10B 43/27 (2023.01); H01L 23/528 (2006.01); H10B 41/10 (2023.01);
U.S. Cl.
CPC ...
H10B 43/27 (2023.02);
Abstract

A method of manufacturing a semiconductor memory device includes forming a preliminary source structure including a source sacrificial layer, forming a preliminary stacked structure including insulating layers and first sacrificial layers over the preliminary source structure, forming a slit passing through the preliminary stacked structure, removing the first sacrificial layers through the slit to define first recess regions between the insulating layers, forming a second sacrificial layer in each of the first recess regions, removing the source sacrificial layer through the slit to define a second recess region, and forming a source channel coupling layer in the second recess region.


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