The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 11, 2026
Filed:
Aug. 16, 2022
Tesla, Inc., Austin, TX (US);
Shishuang Sun, Cupertino, CA (US);
Ganesh Venkataramanan, Sunnyvale, CA (US);
Yang Sun, Palo Alto, CA (US);
Jin Zhao, San Jose, CA (US);
Shaowei Deng, Palo Alto, CA (US);
William Chang, Palo Alto, CA (US);
Mengzhi Pang, Cupertino, CA (US);
Steven Butler, Palo Alto, CA (US);
William A Mcgee, San Jose, CA (US);
Aydin Nabovati, Toronto, CA;
Tesla, Inc., Austin, TX (US);
Abstract
The systems, methods, and devices disclosed herein relate to a multi-layer structures arranged in a vertically orientation. In some embodiments, a computing assembly can include a first cooling system, a first electronics layer, a second cooling system, and a second electronics layer. The first cooling system can be disposed on top of and can be in thermal communication with the first electronics layer. The first electronics layer array includes an array of integrated circuit dies that are in electronic communication with each other in a plane that is orthogonal to power delivery. The first electronics layer can be disposed on top of and can be in thermal communication with the second cooling system, and the second cooling system can be disposed on top of and can be in thermal communication with the second electronics layer. The second electronics layer includes an array of power delivery modules. In some embodiments, at least one layer can use system on wafer packaging.