Decoder circuit and decoding method capable of reducing number of read/write of memory to reduce power consumption

Abstract

A decoding method includes: providing channel value memory to store input data as a channel value; providing sign memory to store a sign value; providing gradient descent bit memory to store differential information of a channel value; providing variable node unit to generate a first output value and a second output value according to the channel value; converting first output value into a converted first output value from variable node domain into check node domain; providing check node unit to generate check-to-variable message according to the converted first output value or the sign value stored in the sign memory; converting the check-to-variable message into a converted check-to-variable message from check node domain into variable node domain and transmitting the converted check-to-variable message into the variable node domain; and, deciding output data according to channel value and differential information stored in gradient descent bit memory.