The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 11, 2026

Filed:

Aug. 17, 2023
Applicant:

Sanechips Technology Co., Ltd., Shenzhen, CN;

Inventors:

Hao Luo, Shenzhen, CN;

Wentao Zhu, Shenzhen, CN;

Yumei Diao, Shenzhen, CN;

Haipeng Zhu, Shenzhen, CN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/0185 (2006.01); H03K 3/356 (2006.01); H03K 19/003 (2006.01); H03M 1/06 (2006.01); H03M 1/66 (2006.01);
U.S. Cl.
CPC ...
H03K 19/018521 (2013.01); H03K 3/356104 (2013.01); H03K 19/00315 (2013.01); H03K 19/01855 (2013.01); H03M 1/0612 (2013.01); H03M 1/662 (2013.01);
Abstract

Provided are a differential latch circuit, a switch driver, and a digital-to-analog conversion circuit. The differential latch circuit includes: a first-stage differential latch circuit (I), a second-stage differential inverter circuit (II), and a low-level shift circuit, a pull-up terminal of a differential positive terminal of the second-stage differential inverter circuit (II) includes a first P-Channel Metal-Oxide-Semiconductor (PMOS) transistor (M) and a second PMOS transistor (M), a pull-down terminal of the differential positive terminal of the second-stage differential inverter circuit (II) includes a third PMOS transistor (M) and a first N-Channel Metal-Oxide-Semiconductor (NMOS) transistor (M), and a circuit structure of a differential negative terminal of the first-stage differential latch circuit (I) is symmetrical to a circuit structure of a differential positive terminal of the first-stage differential latch circuit (I).


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