The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 11, 2026

Filed:

Dec. 28, 2023
Applicant:

SK Hynix Inc., Icheon-si, KR;

Inventors:

Sung Hyun Hwang, Icheon-si, KR;

Jae Yeop Jung, Icheon-si, KR;

Assignee:

SK hynix Inc., Icheon-si, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 16/34 (2006.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/14 (2006.01); G11C 16/24 (2006.01);
U.S. Cl.
CPC ...
G11C 16/3445 (2013.01); G11C 16/08 (2013.01); G11C 16/14 (2013.01); G11C 16/24 (2013.01); G11C 16/0483 (2013.01);
Abstract

A semiconductor device includes a memory cell array and a peripheral circuit. The memory cell array is coupled to a plurality of word lines and a plurality of bit lines. The peripheral circuit performs a deep-erase verification operation to determine whether a target memory cell has a threshold voltage that is lower than a first negative reference voltage by applying a second negative reference voltage that is lower than the first negative reference voltage to the target memory cell.


Find Patent Forward Citations

Hwang, Sung. (2026). Methods and apparatus for performing a deep-erase verification operation (U.S. Patent No. 12706162). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12706162

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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