The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 11, 2026

Filed:

Nov. 26, 2024
Applicant:

Samsung Display Co., Ltd., Yongin-Si, KR;

Inventors:

Soon-Dong Kim, Yongin-si, KR;

Taehoon Kim, Yongin-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/3275 (2016.01); G09G 3/32 (2016.01); G09G 3/3266 (2016.01);
U.S. Cl.
CPC ...
G09G 3/3275 (2013.01); G09G 3/32 (2013.01); G09G 3/3266 (2013.01); G09G 2310/0267 (2013.01); G09G 2310/0275 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/08 (2013.01); G09G 2330/021 (2013.01);
Abstract

At least one stage of a driver includes an input circuit transferring an input signal to a first node in response to at least one of a clock signal and an inverted clock signal, a holding capacitor holding a voltage of the first node, a first inverter generating a voltage of a second node by inverting the voltage of the first node, a second inverter generating a voltage of a third node by inverting the voltage of the second node, a third inverter generating a carry signal by inverting the voltage of the second node, and an output control circuit selectively outputting the voltage of the third node as an output signal in response to an output enable signal. At least one of the first, second, third inverters, and the output control circuit includes a PMOS transistor and an NMOS transistor that are connected in series.


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