The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 11, 2026

Filed:

May. 07, 2024
Applicant:

Nvidia Corporation, Santa Clara, CA (US);

Inventors:

Jay Kishora Gupta, Bangalore, IN;

Vishal Bhatt, Bangalore, IN;

Gosagan Padmanabhan, Bangalore, IN;

Shraddha Gondkar, San Jose, CA (US);

Kaushal Agarwal, Bangalore, IN;

Assignee:

NVIDIA Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/10 (2016.01); G06F 12/1009 (2016.01); G06F 12/1027 (2016.01);
U.S. Cl.
CPC ...
G06F 12/1027 (2013.01); G06F 12/1009 (2013.01);
Abstract

Systems and methods in accordance with the present disclosure can prevent interference of memory operations being performed, for example, by high priority or high safety applications. In various examples, a memory management unit (MMU) can receive, from a client, a request to perform a process. The MMU can select, based at least on an identifier of at least one of the client or the process, a target memory manager of a plurality of memory managers of the MMU. The MMU can cause the target memory manager to perform a memory translation operation for the request.


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