The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 04, 2026

Filed:

Oct. 27, 2023
Applicant:

Vuereal Inc., Waterloo, CA;

Inventors:

Gholamreza Chaji, Kicthener, CA;

Ehsanollah Fathi, Waterloo, CA;

Assignee:

VueReal Inc., Waterloo, CA;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 90/00 (2026.01); H10H 20/01 (2025.01); H10H 20/821 (2025.01); H10H 20/833 (2025.01); H10H 20/84 (2025.01); H10H 20/841 (2025.01); H10H 20/857 (2025.01); H10H 29/14 (2025.01); H10H 20/812 (2025.01); H10H 20/825 (2025.01);
U.S. Cl.
CPC ...
H10W 90/00 (2026.01); H10H 20/0137 (2025.01); H10H 20/018 (2025.01); H10H 20/821 (2025.01); H10H 20/833 (2025.01); H10H 20/84 (2025.01); H10H 20/841 (2025.01); H10H 20/857 (2025.01); H10H 29/14 (2025.01); H10H 20/032 (2025.01); H10H 20/034 (2025.01); H10H 20/0364 (2025.01); H10H 20/812 (2025.01); H10H 20/825 (2025.01);
Abstract

Various embodiments include methods of fabricating an array of self-aligned vertical solid state devices and integrating the devices to a system substrate. The method of fabricating a self-aligned vertical solid state device comprising: providing a semiconductor substrate, depositing a plurality of device layers on the semiconductor substrate, depositing an ohmic contact layer on an upper surface of one of the plurality of device layers, wherein the device layers comprises an active layer and a doped conductive layer, forming a patterned thick conductive layer on the ohmic contact layer; and selectively etching down the doped conductive layer that does not substantially etch the active layer.


Find Patent Forward Citations

Loading…