The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 04, 2026

Filed:

May. 10, 2023
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventor:

Gunho Chang, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 90/00 (2026.01); H10B 80/00 (2026.01); H10W 70/60 (2026.01); H10W 70/63 (2026.01); H10W 72/00 (2026.01); H10W 72/20 (2026.01); H10W 72/30 (2026.01); H10W 74/10 (2026.01); H10W 74/15 (2026.01);
U.S. Cl.
CPC ...
H10W 90/00 (2026.01); H10B 80/00 (2023.02); H10W 70/611 (2026.01); H10W 70/635 (2026.01); H10W 72/07252 (2026.01); H10W 74/111 (2026.01); H10W 72/07353 (2026.01); H10W 72/227 (2026.01); H10W 72/334 (2026.01); H10W 72/337 (2026.01); H10W 74/15 (2026.01); H10W 90/722 (2026.01); H10W 90/724 (2026.01); H10W 90/732 (2026.01); H10W 90/734 (2026.01);
Abstract

A semiconductor package includes a first semiconductor chip, a chip stack on the first semiconductor chip, and a mold layer enclosing the chip stack, on the first semiconductor chip. The chip stack includes second semiconductor chips vertically stacked on the first semiconductor chip, a third semiconductor chip on the second semiconductor chips, and non-conductive layers filling spaces between adjacent ones of the second semiconductor chips. The mold layer fills spaces between the first semiconductor chip and the chip stack, which are spaced apart from each other by a first distance, and between the uppermost one of the second semiconductor chips and the third semiconductor chip, which are spaced apart from each other by a second distance. The second semiconductor chips are spaced apart from each other by a third distance that is smaller than the first distance and the second distance.


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Quick Actions:

Chang, Gunho. (2026). Semiconductor package (U.S. Patent No. 12702067). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12702067

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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