The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 04, 2026

Filed:

Jan. 30, 2023
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Rajen Murugan, Dallas, TX (US);

Yiqi Tang, Allen, TX (US);

Sylvester Ankamah-Kusi, Dallas, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H10W 70/40 (2026.01); H10W 72/00 (2026.01); H10W 72/50 (2026.01); H10W 74/01 (2026.01); H10W 74/10 (2026.01); H10W 90/00 (2026.01);
U.S. Cl.
CPC ...
H10W 70/481 (2026.01); H10W 74/016 (2026.01); H10W 74/129 (2026.01); H10W 72/07554 (2026.01); H10W 72/536 (2026.01); H10W 72/5363 (2026.01); H10W 72/5434 (2026.01); H10W 72/547 (2026.01); H10W 90/728 (2026.01); H10W 90/755 (2026.01); H10W 90/758 (2026.01);
Abstract

A packaged semiconductor device includes a lead frame and a semiconductor die. The semiconductor die has first and second opposing sides, and the first side of the die is mounted to the lead frame. A first set of bond wires and/or bump bonds are configured to electrically couple the die to the lead frame. A passive circuit element is on a substrate, and the substrate is mounted to the second side of the die. A second set of bond wires and/or bump bonds are configured to electrically couple the passive circuit element to the die. A molding material is configured to encapsulate the passive circuit element, the die, and at least a portion of the lead frame.


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