The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 04, 2026

Filed:

Jun. 29, 2023
Applicant:

Texas Instruments Incorported, Dallas, TX (US);

Inventors:

Guangxu Li, Allen, TX (US);

Sylvester Ankamah-Kusi, Dallas, TX (US);

Rajen Murugan, Dallas, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H10W 42/00 (2026.01); H10W 70/05 (2026.01); H10W 70/65 (2026.01); H10W 70/685 (2026.01); H10W 72/00 (2026.01); H10W 72/20 (2026.01); H10W 90/00 (2026.01);
U.S. Cl.
CPC ...
H10W 42/121 (2026.01); H10W 70/05 (2026.01); H10W 70/65 (2026.01); H10W 70/685 (2026.01); H10W 72/072 (2026.01); H10W 72/07236 (2026.01); H10W 72/222 (2026.01); H10W 72/248 (2026.01); H10W 72/252 (2026.01); H10W 90/724 (2026.01);
Abstract

An electronic device includes a multilevel package substrate and a semiconductor die, where the multilevel package substrate has first and second levels in respective first and second planes in a stack, the first level including a first conductive feature, and the second level including a second conductive feature, and the semiconductor die has a conductive peripheral terminal, a conductive interior terminal, a peripheral region, and an interior region. The peripheral region laterally surrounds the interior region and extends laterally between the interior region and the lateral sides of the semiconductor die, the conductive peripheral terminal extends from the peripheral region to the first level, the conductive interior terminal extends from the interior region to the first level, the peripheral terminal is coupled to a peripheral contact portion of the first conductive feature, and the second level has no conductive feature under the peripheral contact portion.


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