The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 04, 2026
Filed:
Feb. 15, 2022
Applicant:
Infineon Technologies Ag, Neubiberg, DE;
Inventors:
Ralf Siemieniec, Villach, AT;
Thomas Aichinger, Faak am See, AT;
Ravi Keshav Joshi, Klagenfurt, AT;
Werner Schustereder, Villach, AT;
Assignee:
Infineon Technologies AG, Neubiberg, DE;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 62/832 (2025.01); H10D 12/01 (2025.01); H10D 30/66 (2025.01); H10D 64/27 (2025.01); H10P 30/20 (2026.01);
U.S. Cl.
CPC ...
H10D 62/8325 (2025.01); H10D 12/031 (2025.01); H10D 30/668 (2025.01); H10D 64/513 (2025.01); H10P 30/2042 (2026.01); H10P 30/21 (2026.01);
Abstract
A silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) and a method for forming a SiC MOSFET are disclosed. In an example, the method includes forming a gate dielectric that adjoins a body region arranged in a semiconductor body, and forming a gate electrode on the gate dielectric. Forming the gate electrode includes forming a first electrode layer, implanting work function adjusting atoms into the first electrode layer, and forming a second electrode layer on the first electrode layer.