The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 04, 2026

Filed:

Dec. 10, 2021
Applicant:

Mitsui Mining & Smelting Co., Ltd., Tokyo, JP;

Inventors:

Toshimi Nakamura, Ageo, JP;

Mikiko Komiya, Ageo, JP;

Yoshinori Matsuura, Ageo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/02 (2006.01); H05K 3/00 (2006.01); H10P 54/00 (2026.01);
U.S. Cl.
CPC ...
H05K 3/0052 (2013.01); H05K 1/0271 (2013.01); H05K 1/0298 (2013.01); H05K 3/0044 (2013.01); H10P 54/00 (2026.01); H05K 1/0266 (2013.01); H05K 2201/09781 (2013.01); H05K 2201/09936 (2013.01); H05K 2203/0228 (2013.01);
Abstract

There is provided a wiring substrate whose mechanical strength, water resistance, humidity resistance, and product yield can be improved. This wiring substrate includes a device region in which a main wiring pattern composed of a metal layer is embedded in an insulating layer; a peripheral region which surrounds a periphery of the device region and in which a dummy wiring pattern composed of a metal layer is embedded in an insulating layer; and an insulating boundary region interposed between the device region and the peripheral region, composed of an insulating layer. The insulating boundary region has a winding shape in which it is possible to draw a virtual straight line alternately traversing the metal layer constituting the dummy wiring pattern and the insulating layer constituting the insulating boundary region, parallel to an inscribed line of at least one side of an outer edge of the device region.


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