Memory device with control elements for unselected defective and unselected non-defective memory blocks

Abstract

A memory device includes a memory cell array including a block including a first transistor connected to a first select gate line, a second transistor connected to a second select gate line, and a plurality of memory cells connected in series between the first and second transistors and each connected to one corresponding word line of a plurality of word lines, and a row control circuit that outputs a control signal for setting the block to be in a selected state or an unselected state based on a result of decoding an address, stores information indicating whether the block is a non-defective block, and controls an electrical state of the second select gate line independently of the first select gate line based on the control signal and the information.