Semiconductor device with shared bit line sense amplifiers

Abstract

A semiconductor device includes a memory cell array including a plurality of memory cells disposed in a matrix, and a peripheral circuit at least partially overlapping the memory cell array in a first direction and including a plurality of sense amplifiers and a plurality of word line drivers configured to drive the plurality of memory cells. The memory cell array further includes a plurality of bit line pairs and a plurality of word lines coupled with the plurality of memory cells. The plurality of bit line pairs are divided into a plurality of groups. Each group of the plurality of groups includes at least two bit line pairs. The at least two bit line pairs included in a same group of the plurality of groups are coupled with a same sense amplifier of the plurality of sense amplifiers.