Circuit snapback and charge diversion for cross-point arrays

Abstract

Technology for reading memory cells in a cross-point memory array. Each memory cell may have a threshold switching selector in series with a programmable resistance memory element. The memory system has control circuitry adjacent to the cross-bar memory array that is used to generate and deliver currents to the cross-bar memory array. The memory system temporarily provides capacitive isolation of the selected memory cell from capacitance of the adjacent circuitry while the snapback current is present. The memory system provides a discharge path to a node between the control circuitry and the selected memory cell during a period in which the capacitive isolation is removed.