The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 04, 2026

Filed:

Mar. 22, 2023
Applicants:

Hefei Boe Joint Technology Co., Ltd., Hefei, CN;

Boe Technology Group Co., Ltd., Beijing, CN;

Inventors:

Zhidong Yuan, Beijing, CN;

Yongqian Li, Beijing, CN;

Liu Wu, Beijing, CN;

Huihui Li, Beijing, CN;

Can Yuan, Beijing, CN;

Cheng Xu, Beijing, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/32 (2016.01); G11C 19/28 (2006.01);
U.S. Cl.
CPC ...
G09G 3/32 (2013.01); G11C 19/287 (2013.01); G09G 2300/0426 (2013.01); G09G 2300/0819 (2013.01); G09G 2300/0842 (2013.01); G09G 2300/0861 (2013.01); G09G 2310/0267 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/08 (2013.01);
Abstract

The present disclosure provides a display device and a display panel. The display panel includes: multiple pixel circuit rows at a side of the substrate, where multiple pixel circuit rows form multiple pixel circuit groups distributed in a column direction, and each pixel circuit group includes at least one pixel circuit row; a gate drive circuit, including multiple shift registers, where at least one shift register is between two adjacent pixel circuit groups. Each of the shift register includes: an output sub-circuit, connected with a first node and a second node, configured to perform output based on potentials of the first node and the second node; and an input sub-circuit, connected with multiple clock signal lines to control the potentials of the first node and the second node based on potentials of multiple clock signal lines.


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