The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 04, 2026

Filed:

Dec. 08, 2023
Applicant:

Memryx Incorporated, Ann Arbor, MI (US);

Inventors:

Timothy Wesley, Ann Arbor, MI (US);

Jacob Botimer, Ann Arbor, MI (US);

Mohammed Zidan, Ann Arbor, MI (US);

Chester Liu, Ann Arbor, MI (US);

Wei Lu, Ann Arbor, MI (US);

Assignee:

MemryX Incorporated, Ann Arbor, MI (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01);
U.S. Cl.
CPC ...
G06F 3/064 (2013.01); G06F 3/0604 (2013.01); G06F 3/0679 (2013.01);
Abstract

A memory processing unit (MPU) includes processing regions and a first memory having memory regions configured in memory blocks. The processing regions are interleaved between the memory regions and include core groups including compute cores. One or more of the core groups of a respective one of the processing regions are coupled between adjacent ones of the memory blocks of adjacent ones of the memory regions. Components of the MPU and dataflow between adjacent compute cores in respective ones of the processing regions through one or more corresponding memory blocks of corresponding memory regions, are configured based on one or more of an impact of a number of parameters and a number of layers of one or more neural network models on memory balance, core utilization and memory reuse on bandwidth balance, design points, supported operations, target models, and supported memory organizations.


Find Patent Forward Citations

Loading…