The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 04, 2026

Filed:

Jun. 28, 2024
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Vinay Patel, Stouffville, CA;

Nitin Makhija, San Jose, CA (US);

Pradeep Kanapathipillai, Campbell, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/3234 (2019.01);
U.S. Cl.
CPC ...
G06F 1/3243 (2013.01);
Abstract

Controlling instruction issue rate using credit-based mechanisms in processor devices is disclosed herein. In some aspects, a processor device comprises a credit logic circuit that is communicatively coupled to a reservation station (RS) circuit, and that comprises a credit counter. The credit logic circuit receives an instruction issue indication for an instruction from the RS circuit during a time interval. The credit logic circuit decrements a value of a credit counter. The credit logic circuit also determines whether the value of the credit counter equals or is less than a blocking threshold, and, if so, asserts a block signal to the RS circuit. The RS circuit is configured to receive the block signal, and, responsive to receiving the block signal, block further instruction issuance during the time interval.


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