The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 04, 2026

Filed:

Oct. 04, 2024
Applicant:

Signature Ip Corporation, Milpitas, CA (US);

Inventors:

Shivam Mehra, New Delhi, IN;

Parag Bhatt, San Jose, CA (US);

Michael Loe Fernandez, Quezon City, PH;

Kishore Mishra, Santa Clara, CA (US);

Purna Mohanty, Sunnyvale, CA (US);

Assignee:

Signature IP Corporation, Milpitas, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01); G01R 31/317 (2006.01);
U.S. Cl.
CPC ...
G01R 31/31707 (2013.01); G01R 31/31712 (2013.01);
Abstract

Techniques for the testing of devices are disclosed. A testing environment is accessed. The testing environment includes an instruction RAM, an instruction fetch and decode unit (FAD), a code exerciser, a command interface, and a trace RAM. A device under test (DUT) is accessible by the command interface. The testing environment includes a test instruction set architecture (TISA). A test sequence is programmed by a user. The test sequence includes one or more instructions from within the TISA. The test sequence is stored in the instruction RAM. A first instruction is fetched by the FAD. The fetching includes decoding the first instruction. The first instruction is translated by the code exerciser. The translating produces a first packetized communication, which is sent to the DUT. A first packetized response is received by the command interface from the DUT and is reported to the user.


Find Patent Forward Citations

Mehra, Shivam. (2026). Flexible test instruction set architecture (U.S. Patent No. 12699131). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12699131

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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