The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 28, 2026
Filed:
Feb. 15, 2021
Sony Semiconductor Solutions Corporation, Kanagawa, JP;
Naoto Sasaki, Nagasaki, JP;
Kenichi Saitou, Nagasaki, JP;
Yusuke Hayashi, Nagasaki, JP;
Atsuhiko Yamada, Nagasaki, JP;
Takushi Shigetoshi, Kanagawa, JP;
Takuya Ooi, Nagasaki, JP;
Sony Semiconductor Solutions Corporation, Kanagawa, JP;
Abstract
A parasitic capacitance of a wiring arranged on a back surface side of a semiconductor substrate is reduced. A semiconductor apparatus includes a semiconductor substrate, a back surface side wiring, a through wiring, and a separation region. In the semiconductor substrate, a semiconductor element and a front surface side wiring connected to the semiconductor element are arranged on a front surface side. The back surface side wiring is arranged on a back surface side of the semiconductor substrate. The through wiring is arranged in a through hole formed in the semiconductor substrate to connect the front surface side wiring and the back surface side wiring. The separation region is arranged between the semiconductor substrate and the back surface side wiring.