The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 28, 2026

Filed:

Apr. 18, 2024
Applicant:

Toppan Holdings Inc., Tokyo, JP;

Inventor:

Tomoyuki Ishii, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/03 (2006.01); H05K 3/00 (2006.01); H05K 3/46 (2006.01);
U.S. Cl.
CPC ...
H05K 1/0306 (2013.01); H05K 3/0017 (2013.01); H05K 3/4644 (2013.01); H05K 2201/0266 (2013.01); H05K 2201/0338 (2013.01); H05K 2201/09154 (2013.01); H05K 2203/0548 (2013.01); H05K 2203/1105 (2013.01);
Abstract

A wiring board includes: a substrate; a first seed layer provided on the substrate; a first conductive layer provided on the first seed layer; a first insulating layer provided on the first conductive layer; a second seed layer provided on the first insulating layer; and a second conductive layer provided on the second seed layer. An area of the first insulating layer is smaller than an area of the first conductive layer. An area of the second conductive layer is smaller than the area of the first insulating layer. A region of the first insulating layer not overlapping the second conductive layer includes a first region surrounding the second conductive layer and a second region outside the first region. A surface roughness of the second region is larger than a surface roughness of the first region.


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