Memory structure, storage method, entropy decoding method, chip, device, and storage medium

Abstract

Disclosed are a memory structure, a storage method, an entropy decoding method, a chip, a device, and a storage medium. The memory structure includes: a row storage circuit including a plurality of row storage components in a number identical to a number of rows of a decoding unit, where the row storage components correspond one-to-one to ordinates of the decoding unit, and each row storage component is configured to store a coding coefficient under a corresponding ordinate, and an abscissa of the coding coefficient; a column storage circuit including a plurality of column storage components in a number identical to a number of columns of the decoding unit, where the column storage components correspond one-to-one to abscissas of the decoding unit, and each column storage component is configured to store a coding coefficient under a corresponding abscissa, and an ordinate of the stored coding coefficient; and diagonal storage components in a number equaling 1 subtracted from the sum of the number of rows and the number of columns of the decoding unit, where each diagonal storage component is configured to store a coding coefficient on a corresponding diagonal position line, and an abscissa or an ordinate of the stored coding coefficient. According to the disclosure, an occupied area of the memory structure is reduced.