Decoding circuit, decoding method and computer program

Abstract

Provided is a decoding circuit used for coherent digital signal processing, including: a distributor that distributes a decoding metric obtained by demodulating transmission data transmitted from a transmission device to each of a plurality of lanes on the basis of information on noise generated in a communication channel and a received signal; a first likelihood calculation circuit that is provided in one of the plurality of lanes and calculates a first logarithmic likelihood ratio using the decoding metric distributed by the distributor; a decoding unit that performs error correction decoding using the first logarithmic likelihood ratio and acquires an error-corrected code word; one or more second likelihood calculation circuits that are provided in a lane different from the lane in which the first likelihood calculation circuit is provided among the plurality of lanes, calculate a second logarithmic likelihood ratio on the basis of the decoding metric distributed by the distributor and the acquired code word, and perform hard decision; a combining unit that combines an output of the decoding unit and an output of the one or more second likelihood calculation circuits; and an outer code decoding unit that decodes an outer code.