The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 28, 2026
Filed:
Jan. 29, 2025
Texas Instruments Incorporated, Dallas, TX (US);
Ramsin Ziazadeh, San Jose, CA (US);
Sonam Sadhukhan, Santa Clara, CA (US);
TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US);
Abstract
An example apparatus includes an inverter having a first terminal and a second terminal coupled to an enable terminal. The apparatus includes a first transistor having a control terminal, a first terminal, and a second terminal, the control terminal coupled to the first terminal of the inverter, the first terminal coupled to a supply terminal. The apparatus includes a second transistor having a control terminal, a first terminal, and a second terminal, the first terminal coupled to the second terminal of the first transistor. The apparatus includes an inductor having a first terminal coupled to the second terminal of the second transistor and a second terminal coupled to the control terminal of the second transistor. The apparatus includes a capacitor having a first terminal coupled to the second terminal of the second transistor and a second terminal coupled to the control terminal of the second transistor. The apparatus includes a third transistor having a control terminal, a first terminal, and a second terminal, the control terminal coupled to the first terminal of the inductor and the first terminal of the capacitor, the second terminal coupled to the second terminal of the inductor and the second terminal of the capacitor. The apparatus includes a fourth transistor having a control terminal coupled to the enable terminal, a first terminal coupled to a ground terminal, and a second terminal coupled to the first terminal of the third transistor.