The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 28, 2026

Filed:

Feb. 27, 2023
Applicant:

Sunrise Memory Corporation, San Jose, CA (US);

Inventor:

Eli Harari, Saratoga, CA (US);

Assignee:

SUNRISE MEMORY CORPORATION, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 51/10 (2023.01); G11C 16/04 (2006.01); H10B 51/20 (2023.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 30/69 (2025.01); H10D 64/68 (2025.01);
U.S. Cl.
CPC ...
G11C 16/0483 (2013.01); H10B 51/10 (2023.02); H10B 51/20 (2023.02); H10D 30/0415 (2025.01); H10D 30/6755 (2025.01); H10D 30/701 (2025.01); H10D 64/689 (2025.01);
Abstract

A memory structure including three-dimensional NOR memory strings and method of fabrication is disclosed. In some embodiments, a memory structure includes randomly accessible ferroelectric storage transistors organized as horizontal NOR memory strings. The NOR memory strings are formed over a semiconductor substrate in multiple scalable memory stacks of thin-film storage transistors. The ferroelectric storage transistors are junctionless field-effect transistors having a ferroelectric polarization layer formed adjacent a semiconductor oxide layer as the channel region. The three-dimensional memory stacks are manufactured in a process that uses a sacrificial layer and access shafts to perform channel separation through a backside selective etch process.


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