The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 28, 2026

Filed:

Feb. 29, 2024
Applicant:

Arm Limited, Cambridge, GB;

Inventors:

Navin Agarwal, Bangalore, IN;

Yattapu Viswanatha Reddy, Bangalore, IN;

Renu Rawat, Bangalore, IN;

Georgy Jacob, Bangalore, IN;

Avinash Merugu, Bangalore, IN;

Yanduri Kaliamma, Krishna, IN;

Daksheshkumar Maganbhai Malaviya, Bangalore, IN;

Ashish Kumar Srivastava, Bangalore, IN;

Yuvaraj Munirathinam, Bangalore, IN;

Tangudu Sivaramgupta, Bangalore, IN;

Rajiv Kumar Sisodia, Bangalore, IN;

Prashantkumar Jayantilal Vaghasia, Austin, TX (US);

Vishal Vinay Thakre, Austin, TX (US);

Jaspreet Singh, Bangalore, IN;

Munish Kumar, Greater Noida West, IN;

Assignee:

Arm Limited, Cambridge, GB;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/22 (2006.01); G11C 11/4076 (2006.01); G11C 11/4096 (2006.01); G11C 29/00 (2006.01); G11C 7/10 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4076 (2013.01); G11C 7/22 (2013.01); G11C 11/4096 (2013.01); G11C 29/842 (2013.01); G11C 7/1072 (2013.01);
Abstract

According to one implementation, a method includes determining a self-timed path (STP) circuit based on a first resistor-capacitor (RC) delay and a logic delay, wherein the first RC delay includes a delay associated with a first dummy wordline (DWL) and a dummy bitline (DBL); and extending the STP circuit based on a second RC delay, wherein the second RC delay includes a delay associated with an extended DWL.


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