Memory device and operation method for data movement within memory sections and through external interfaces of memory device

Abstract

A memory device is provided, which includes a memory array and data transfer circuits. The memory array is divided into multiple memory sections, each containing memory cells. A data transfer circuit is placed between two memory sections. Through this data transfer circuit, data can move either from all or from a selected set of bit lines or bit-line pairs within a section to adjacent memory sections, or between data interfaces other than the bit lines or bit-line pairs in the memory sections. Data signals from all or a selected set of bit lines or bit-line pairs in the memory sections are sensed, latched, buffered, and repeated for data transfer or for executing logic operations via the data transfer circuit. These data movements and logic operations within the memory device can be executed in parallel. A method for controlling and operating such a memory device is also provided.