The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 28, 2026

Filed:

Sep. 13, 2024
Applicant:

Kioxia Corporation, Tokyo, JP;

Inventors:

Takafumi Masuda, Kawasaki Kanagawa, JP;

Mutsumi Okajima, Yokkaichi Mie, JP;

Nobuyoshi Saito, Tokyo, JP;

Keiji Ikeda, Kawasaki Kanagawa, JP;

Assignee:

Kioxia Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/06 (2006.01); G11C 11/22 (2006.01); H10B 51/10 (2023.01); H10B 51/20 (2023.01);
U.S. Cl.
CPC ...
G11C 5/06 (2013.01); G11C 11/2273 (2013.01); H10B 51/10 (2023.02); H10B 51/20 (2023.02);
Abstract

A semiconductor memory device includes: a first via-wiring extending in a first direction; first semiconductor layers arranged in the first direction and electrically connected to the first via-wiring; memory portions arranged in the first direction and electrically connected to the first semiconductor layers; first gate electrodes arranged in the first direction and opposed to the plurality of first semiconductor layers; first wirings arranged in the first direction and electrically connected to the plurality of first gate electrodes; second semiconductor layers arranged in the first direction and electrically connected to the first wirings; second gate electrodes arranged in the first direction and opposed to the second semiconductor layers; a second via-wiring extending in the first direction and electrically connected to the plurality of second gate electrodes; and second wirings arranged in the first direction and electrically connected to the second semiconductor layers.


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