The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 28, 2026
Filed:
Jul. 01, 2022
Applicant:
Altera Corporation, San Jose, CA (US);
Inventors:
Assignee:
Altera Corporation, San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/343 (2020.01); G06F 30/20 (2020.01); G06F 30/327 (2020.01); G06F 30/331 (2020.01); G06F 30/347 (2020.01);
U.S. Cl.
CPC ...
G06F 30/343 (2020.01); G06F 30/20 (2020.01); G06F 30/327 (2020.01); G06F 30/331 (2020.01); G06F 30/347 (2020.01);
Abstract
Systems or methods of the present disclosure may provide a compilation design method that uses cloud computing resources and/or distributed computing resources to compile initial user designs. The initial user design for the programmable logic device may be partitioned into multiple designs for compilation based on periphery logic and core fabric logic. The compilation design method implements partition-level time budgeting and constraint generation using full device timing analysis. The final placed and routed netlist and bitstream SOF is generated by merging the placed and routed netlist and bitstream SOF of individual partition designs.