Hybrid switching architecture for serdes communication channels in reconfigurable hardware modeling circuits

Abstract

Various aspects of the present disclosed technology relate to hybrid static and dynamic switching in a reconfigurable hardware modeling circuit for flexible and low latency communications. The reconfigurable hardware modeling circuit comprises serializer circuitry and deserializer circuitry for one or more communication ports, wherein the serializer circuitry has first sub-channels for receiving data to be sent out from the reconfigurable hardware modeling circuit, and the deserializer circuitry has second sub-channels for outputting data received by the reconfigurable hardware modeling circuit. The reconfigurable hardware modeling circuit also comprises static switching circuitry configurable to couple each of first zero or one or more sub-channels in the first sub-channels with one of signal sources comprising the second sub-channels and dynamic switching circuitry configurable to couple, in a time-division multiplexing mode, each of second zero or one or more sub-channels in the first sub-channels with more than one of the signal sources.