The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 21, 2026

Filed:

Jan. 12, 2023
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventor:

Myungsam Kang, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 70/69 (2026.01); H10W 70/05 (2026.01); H10W 74/10 (2026.01); H10W 90/00 (2026.01); H10W 74/00 (2026.01);
U.S. Cl.
CPC ...
H10W 70/69 (2026.01); H10W 70/095 (2026.01); H10W 74/117 (2026.01); H10W 90/701 (2026.01); H05K 2203/1316 (2013.01); H10W 74/00 (2026.01); H10W 90/724 (2026.01);
Abstract

A semiconductor package includes stacked wiring layers, a lower substrate pad on a bottom surface of a lowermost wiring layer, a protection layer covering the lower substrate pad on the bottom surface of the lowermost wiring layer, a dielectric layer on a top surface of an uppermost wiring layer, an upper substrate pad on the dielectric layer, a semiconductor chip on the upper substrate pad, and a molding layer covering the semiconductor chip on the uppermost wiring layer. Each of the wiring layers includes a dielectric pattern and a wiring pattern therein. The protection layer has openings that expose the lower substrate pad. A thickness of the dielectric layer is less than that of the dielectric pattern in the wiring layers. A thickness of the upper substrate pad is less than that of the wiring pattern in the wiring layers.


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