The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 21, 2026

Filed:

Sep. 08, 2023
Applicant:

Em Microelectronic—marin SA, Marin, CH;

Inventors:

Christophe Entringer, Corcelles-près-Concise, CH;

Yves Dupraz, Valeyres sous Montagny, CH;

Pierre Muller, Marin-Epagnier, CH;

Zeng Wang, Bienne, CH;

Alexis Durand, Cudrefin, CH;

Arthur Hugh Macdougall, Cornaux, CH;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10W 42/00 (2026.01); H10P 54/00 (2026.01); H10W 74/10 (2026.01); H10W 72/20 (2026.01);
U.S. Cl.
CPC ...
H10W 42/00 (2026.01); H10P 54/00 (2026.01); H10W 74/147 (2026.01); H10W 72/252 (2026.01);
Abstract

A semiconductor wafer () including a plurality of chips () and a separation zone () spacing the semiconductor chips () from each other in this wafer (), such a separation zone () extending from a front face () to an opposite backside face () of this wafer (), this separation zone () includes a scribe line () configured to be diced using plasma etching and an inlet area () of this scribe line (), the inlet () being delimitated by free ends of plasma etch-resistant material layers () extending each from a peripheral wall () of a functional part () of a chip () into the scribe line () by overlapping a top of a seal ring () of this chip ().


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